Researchers from the University of California, Santa Barbara, will be presenting a paper focused on CMOS-compatible graphene interconnects next month at the world-renowned semiconductor-technology conference - the IEEE International Electron Devices Meeting (Dec. 1-5 in San Francisco).

The team has shown that integrating graphene into the interconnect scheme holds the promise of increasing performance and limiting power consumption in next-generation CMOS ICs, as graphene offers high conductivity and is not prone to electromigration.

One of the main challenges for practical implementations are the high temperatures typically needed to form graphene (800-1000ºC), which would damage the active devices already fabricated at the front-end-of-the-line.

University of California-Santa Barbara researchers will report on a new approach in which a low-temperature (300ºC) pressure-assisted solid-phase diffusion process enables the growth and doping of multi-level CMOS-compatible graphene nanoribbons.

These nanoribbons demonstrated a markedly lower contact resistance (100ºC.

These results point to a practical and industry-compatible approach toward exploiting the unique electrical properties of graphene in silicon-based CMOS ICs.